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19-2413; Rev 1; 2/03
2-Wire-Interfaced, 2.5V to 5.5V, 20-Port or 28-Port I/O Expander
General Description
The MAX7300 compact, serial-interfaced, I/O expansion peripheral provides microprocessors with up to 28 ports. Each port is individually user configurable to either a logic input or logic output. Each port can be configured as either a push-pull logic output capable of sinking 10mA and sourcing 4.5mA, or a Schmitt logic input with optional internal pullup. Seven ports feature configurable transition detection logic, which generates an interrupt upon change of port logic level. The MAX7300 is controlled through an I2CTM-compatible 2-wire serial interface, and uses four-level logic to allow 16 I2C addresses from only two select pins. The MAX7300AAX and MAX7300AGL have 28 ports and are available in 36-pin SSOP and 40-pin QFN packages, respectively. The MAX7300AAI and MAX7300ANI have 20 ports and are available in 28-pin SSOP and 28pin DIP packages, respectively.
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Features
o 400kbps I C-Compatible Serial Interface o 2.5V to 5.5V Operation o -40C to +125C Temperature Range o 20 or 28 I/O Ports, Each Configurable as Push-Pull Logic Output Schmitt Logic Input Schmitt Logic Input with Internal Pullup o 11A (max) Shutdown Current o Logic Transition Detection for Seven I/O Ports
MAX7300
Ordering Information
PART MAX7300ANI MAX7300AAI MAX7300AAX MAX7300AGL TEMP RANGE -40C to +125C -40C to +125C -40C to +125C -40C to +125C PIN-PACKAGE 28 DIP 28 SSOP 36 SSOP 40 QFN
Applications
White Goods Automotive Industrial Controllers System Monitoring
Typical Operating Circuit Pin Configurations
TOP VIEW
ISET 1 GND 2 GND 3 AD0 4 P12 5 P13 6 P14 7 P15 8 P16 9 P17 10 P18 11 P19 12 P20 13 P21 14 28 V+ 27 AD1 26 SCL 25 SDA 24 P31
35 AD1 4 AD0 33 SDA 34 SCL 31 P31 29 P30 27 P29 25 P28 24 P27 23 P26 22 P25 21 P24 39k 47nF 3 GND 2 GND 1 ISET 3V 36 V+ P4 32 P5 30 P6 28 P7 26 P8 5 P9 7 P10 9 P11 11 I/O 4 I/O 5 I/O 6 I/O 7 I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15 I/O 16 I/O 17 I/O 18 I/O 19 I/O 20 I/O 21 I/O 22 I/O 23 I/O 24 I/O 25 I/O 26 I/O 27 I/O 28 I/O 29 I/O 30 I/O 31
MAX7300AAX
MAX7300
23 P30 22 P29 21 P28 20 P27 19 P26 18 P25 17 P24 16 P23 15 P22
DATA CLOCK
P12 6 P13 8 P14 10 P15 12 P16 13 P17 14 P18 15 P19 16 P20 17 P21 18 P22 19 P23 20
SSOP/DIP
Pin Configurations continued at end of data sheet.
I 2C is a trademark of Philips Corp.
________________________________________________________________ Maxim Integrated Products
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2-Wire-Interfaced, 2.5V to 5.5V, 20-Port or 28-Port I/O Expander MAX7300
ABSOLUTE MAXIMUM RATINGS
Voltage (with respect to GND) V+ .............................................................................-0.3V to +6V SCL, SDA, AD0, AD1................................................-0.3V to +6V All Other Pins................................................-0.3V to (V+ + 0.3V) P4-P31 Current ................................................................30mA GND Current .....................................................................800mA Continuous Power Dissipation (TA = +70C) 28-Pin PDIP (derate 20.8mW/C above +70C).........1667mW 28-Pin SSOP (derate 9.5mW/C above +70C) ...........762mW 36-Pin SSOP (derate 11.8mW/C above +70C) .........941mW 40-Pin QFN (derate 23.25mW/C aboveTA = +70C)..1860mW Operating Temperature Range (TMIN to TMAX) ...............................................-40C to +125C Junction Temperature ......................................................+150C Storage Temperature Range .............................-65C to +150C Lead Temperature (soldering, 10s) .................................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(Typical Operating Circuit, V+ = 2.5V to 5.5V, TA = TMIN to TMAX, unless otherwise noted.) (Note 1)
PARAMETER Operating Supply Voltage Shutdown Supply Current SYMBOL V+ ISHDN All digital inputs at V+ or GND TA = +25C TA = -40C to +85C TMIN to TMAX All ports programmed TA = +25C as outputs high, no TA = -40C to +85C load, all other inputs at V+ or GND TMIN to TMAX All ports programmed TA = +25C as outputs low, no TA = -40C to +85C load, all other inputs at V+ or GND TMIN to TMAX All ports programmed TA = +25C as inputs without pullup, ports, and all TA = -40C to +85C other inputs at V+ or TMIN to TMAX GND 180 CONDITIONS MIN 2.5 5.5 TYP MAX 5.5 8 10 11 240 260 280 170 210 230 240 110 135 140 145 A A A A UNITS V
Operating Supply Current
IGPOH
Operating Supply Current
IGPOL
Operating Supply Current
IGPI
INPUTS AND OUTPUTS Logic High Input Voltage Port Inputs Logic Low Input Voltage Port Inputs Input Leakage Current GPIO Input Internal Pullup to V+ Hysteresis Voltage GPIO Inputs VIH VIL IIH, IIL IPU VI GPIO inputs without pullup, VPORT = V+ to GND V+ = 2.5V V+ = 5.5V -100 12 80 1 19 120 0.3 0.7 x V+ 0.3 x V+ +100 30 180 V V nA A V
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2-Wire-Interfaced, 2.5V to 5.5V, 20-Port or 28-Port I/O Expander
ELECTRICAL CHARACTERISTICS (continued)
(Typical Operating Circuit, V+ = 2.5V to 5.5V, TA = TMIN to TMAX, unless otherwise noted.) (Note 1)
PARAMETER SYMBOL CONDITIONS GPIO outputs, ISOURCE = 2mA, TA = -40C to +85C GPIO outputs, ISOURCE = 1mA, TA = TMIN to TMAX (Note 2) VPORT = 0.6V Port configured output low, shorted to V+ MIN V+ 0.7 V V+ 0.7 2 2.75 0.7 x V+ 0.3 x V+ -50 (Note 2) VOL ISINK = 6mA +50 10 0.4 10 11 18 20 mA mA V V nA pF V TYP MAX UNITS
MAX7300
Output High Voltage
VOH
Port Sink Current Output Short-Circuit Current Input High-Voltage SDA, SCL, AD0, AD1 Input Low-Voltage SDA, SCL, AD0, AD1 Input Leakage Current SDA, SCL Input Capacitance Output Low-Voltage SDA
IOL IOLSC VIH VIL IIH, IIL
TIMING CHARACTERISTICS (Figure 2)
(V+ = 2.5V to 5.5V, TA = TMIN to TMAX, unless otherwise noted.) (Note 1)
PARAMETER Serial Clock Frequency Bus Free Time Between a STOP and a START Condition Hold Time (Repeated) START Condition Repeated START Condition Setup Time STOP Condition Setup Time Data Hold Time Data Setup Time SCL Clock Low Period SCL Clock High Period Rise Time of Both SDA and SCL Signals, Receiving Fall Time of Both SDA and SCL Signals, Receiving Fall Time of SDA Transmitting Pulse Width of Spike Suppressed Capacitive Load for Each Bus Line SYMBOL fSCL tBUF tHD, STA tSU, STA tSU, STO tHD, DAT tSU, DAT tLOW tHIGH tR tF tF,TX tSP Cb (Notes 2, 4) (Notes 2, 4) (Notes 2, 5) (Notes 2, 6) (Note 2) 0 (Note 3) 1.3 0.6 0.6 0.6 15 100 1.3 0.7 20 + 0.1Cb 20 + 0.1Cb 20 + 0.1Cb 300 300 250 50 400 900 CONDITIONS MIN TYP MAX 400 UNITS kHz s s s s ns ns s s ns ns ns ns pF
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2-Wire-Interfaced, 2.5V to 5.5V, 20-Port or 28-Port I/O Expander MAX7300
TIMING CHARACTERISTICS (Figure 2) (continued)
(V+ = 2.5V to 5.5V, TA = TMIN to TMAX, unless otherwise noted.) (Note 1) Note 1: All parameters tested at TA = +25C. Specifications over temperature are guaranteed by design. Note 2: Guaranteed by design. Note 3: A master device must provide a hold time of at least 300ns for the SDA signal (referred to VIL of the SCL signal) in order to bridge the undefined region of SCL's falling edge. Note 4: Cb = total capacitance of one bus line in pF. tR and tF measured between 0.3V+ and 0.7V+. Note 5: ISINK 6mA. Cb = total capacitance of one bus line in pF. tR and tF measured between 0.3V+ and 0.7V+. Note 6: Input filters on the SDA and SCL inputs suppress noise spikes less than 50ns.
__________________________________________Typical Operating Characteristics
(RISET = 39k, TA = +25C, unless otherwise noted.)
OPERATING SUPPLY CURRENT vs. TEMPERATURE
MAX7300 toc01
SHUTDOWN SUPPLY CURRENT vs. TEMPERATURE
MAX7300 toc02
OPERATING SUPPLY CURRENT vs. V+ (OUTPUTS UNLOADED)
MAX7300 toc03
0.40 0.36 0.32 SUPPLY CURRENT (mA) 0.28 0.24 0.20 0.16 0.12 0.08 0.04 0 -40.0 -12.5 15.0 42.5 70.0 97.5 ALL PORTS INPUT HIGH ALL PORTS OUTPUT (1) ALL PORTS OUTPUT (0) V+ = 2.5V TO 5.5V NO LOAD
8 V+ = 5.5V 7 SUPPLY CURRENT (A) V+ = 3.3V 6
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SUPPLY CURRENT ( mA)
ALL PORTS OUTPUT (1) ALL PORTS OUTPUT (0)
5
V+ = 2.5V
4 0.1 -40.0 -12.5 15.0 42.5 70.0 97.5 125.0 2.0 2.5 3.0 3.5
ALL PORTS INPUT (PULLUPS DISABLED) 4.0 4.5 5.0 5.5
3 125.0 TEMPERATURE (C) TEMPERATURE (C)
V+ (V)
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2-Wire-Interfaced, 2.5V to 5.5V, 20-Port or 28-Port I/O Expander
Typical Operating Characteristics (continued)
(RISET = 39k, TA = +25C, unless otherwise noted.)
GPO SINK CURRENT vs. TEMPERATURE (OUTPUT = 0)
MAX7300 toc04
MAX7300
GPO SOURCE CURRENT vs. TEMPERATURE (OUTPUT = 1)
VPORT = 1.4V 8 PORT SOURCE CURRENT (mA) 7 6 5 4 3 2 V+ = 5.5V V+ = 3.3V V+ = 2.5V
MAX7300 toc05
18 16 PORT SINK CURRENT (mA) 14 12 10 8 6 4 2 -40.0 -12.5 15.0 42.5 70.0 97.5 V+ = 2.5V TO 5.5V, VPORT = 0.6V
9
125.0
-40.0
-12.5
15.0
42.5
70.0
97.5
125.0
TEMPERATURE (C)
TEMPERATURE (C)
GPI PULLUP CURRENT vs. TEMPERATURE
MAX7300 toc06
GPO SHORT-CIRCUIT CURRENT vs. TEMPERATURE
MAX7300 toc07
1000
100
PULLUP CURRENT (A)
V+ = 5.5V
PORT CURRENT (mA)
GPO = 0, PORT SHORTED TO V+ 10
100 V+ = 3.3V
V+ = 2.5V 10 -40.0 -12.5 15.0 42.5 70.0 97.5 125.0 TEMPERATURE (C) 1 -40.0
GPO = 1, PORT SHORTED TO GND -12.5 15.0 42.5 70.0 97.5 125.0
TEMPERATURE (C)
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2-Wire-Interfaced, 2.5V to 5.5V, 20-Port or 28-Port I/O Expander MAX7300
Pin Description
PIN SSOP/DIP 1 2, 3 4 5-24 -- 25 26 27 28 SSOP 1 2, 3 4 -- 5-32 33 34 35 36 QFN 36 37, 38, 39 40 -- 1-10, 12-19, 21-30 32 33 34 35 NAME ISET GND AD0 P12-P31 P4-P31 SDA SCL AD1 V+ FUNCTION Bias Current Setting. Connect ISET to GND through a resistor (RISET) value of 39k to 120k. Ground Address Input 0. Sets device slave address. Connect to either GND, V+, SCL, SDA to give four logic combinations. See Table 3. I/O Ports. P12 to P31 can be configured as push-pull outputs, CMOSlogic inputs, or CMOS-logic inputs with weak pullup resistor. I/O Ports. P4 to P31 can be configured as push-pull outputs, CMOSlogic inputs, or CMOS-logic inputs with weak pullup resistor. I2C-Compatible Serial Data I/O I2C-Compatible Serial Clock Input Address Input 1. Sets device slave address. Connect to either GND, V+, SCL, SDA to give four logic combinations. See Table 3. Positive Supply Voltage. Bypass V+ to GND with minimum 0.047F capacitor.
Detailed Description
The MAX7300 general-purpose input/output (GPIO) peripheral provides up to 28 I/O ports, P4 to P31, controlled through an I2C-compatible serial interface. The ports can be configured to any combination of logic inputs and logic outputs, and default to logic inputs on power-up. Figure 1 is the MAX7300 functional diagram. Any I/O port can be configured as a push-pull output (sinking 10mA, sourcing 4.5mA), or a Schmitt-trigger logic input. Each input has an individually selectable internal pullup resistor. Additionally, transition detection allows seven ports (P24 to P30) to be monitored in any maskable combination for changes in their logic status. A detected transition is flagged through a status register bit, as well as an interrupt pin (port P31), if desired. The port configuration registers individually set the 28 ports, P4 to P31, as GPIO. A pair of bits in registers 0x09 through 0x0F sets each port's configuration (Tables 1 and 2). The 36-pin MAX7300AAX and 40-pin MAX7300AGL have 28 ports, P4 to P31. The 28-pin MAX7300ANI and MAX7300AAI have only 20 ports available, P12 to P31. The eight unused ports should be configured as outputs on power-up by writing 0x55 to registers 0x09 and
0x0A. If this is not done, the eight unused ports remain as floating inputs and quiescent supply current rises, although there is no damage to the part.
Register Control of I/O Ports Across Multiple Drivers
The MAX7300 offers 20 or 28 I/O ports, depending on package choice. Two addressing methods are available. Any single port (bit) can be written (set/cleared) at once; or, any sequence of eight ports can be written (set/cleared) in any combination at once. There are no boundaries; it is equally acceptable to write P0 to P7, P1 to P8, or P31 to P38 (P32 to P38 are nonexistent, so the instructions to these bits are ignored). Shutdown When the MAX7300 is in shutdown mode, all ports are forced to inputs, and the pullup current sources are turned off. Data in the port and control registers remain unaltered, so port configuration and output levels are restored when the MAX7300 is taken out of shutdown. The MAX7300 can still be programmed while in shutdown mode. For minimum supply current in shutdown mode, logic inputs should be at GND or V+ potential. Shutdown mode is exited by setting the S bit in the configuration register (Table 8).
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2-Wire-Interfaced, 2.5V to 5.5V, 20-Port or 28-Port I/O Expander MAX7300
Table 1. Port Configuration Map
REGISTER Port Configuration for P7, P6, P5, P4 Port Configuration for P11, P10, P9, P8 Port Configuration for P15, P14, P13, P12 Port Configuration for P19, P18, P17, P16 Port Configuration for P23, P22, P21, P20 Port Configuration for P27, P26, P25, P24 Port Configuration for P31, P30, P29, P28 ADDRESS CODE (HEX) 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F REGISTER DATA D7 P7 P11 P15 P19 P23 P27 P31 D6 D5 P6 P10 P14 P18 P22 P26 P30 D4 D3 P5 P9 P13 P17 P21 P25 P29 D2 D1 P4 P8 P12 P16 P20 P24 P28 D0
Table 2. Port Configuration Matrix
MODE FUNCTION PORT REGISTER DO NOT USE THIS SETTING Output Input Input GPIO Output GPIO Input without Pullup GPIO Input with Pullup Written Low Written High Reading Port Reading Port Active-low logic output Active-high logic output Schmitt logic output Schmitt logic input with pullup PIN BEHAVIOR ADDRESS CODE (HEX) 0x09 to 0x0F 0x09 to 0x0F 0x09 to 0x0F 0x09 to 0x0F PORT CONFIGURATION BIT PAIR UPPER 0 0 1 1 LOWER 0 1 0 1
Serial Interface
Serial Addressing
The MAX7300 operates as a slave that sends and receives data through an I2C-compatible 2-wire interface. The interface uses a serial data line (SDA) and a serial clock line (SCL) to achieve bidirectional communication between master(s) and slave(s). A master (typically a microcontroller) initiates all data transfers to and from the MAX7300, and generates the SCL clock that synchronizes the data transfer (Figure 2). The MAX7300 SDA line operates as both an input and an open-drain output. A pullup resistor, typically 4.7k, is required on SDA. The MAX7300 SCL line operates only as an input. A pullup resistor, typically 4.7k, is required on SCL if there are multiple masters on the 2wire interface, or if the master in a single-master system has an open-drain SCL output. Each transmission consists of a START condition (Figure 3) sent by a master, followed by the MAX7300 7-bit slave address plus R/ W bit (Figure 6), a register address byte, one or more data bytes, and finally a STOP condition (Figure 3).
Start and Stop Conditions
Both SCL and SDA remain high when the interface is not busy. A master signals the beginning of a transmission with a START (S) condition by transitioning SDA from high to low while SCL is high. When the master has finished communicating with the slave, it issues a STOP (P) condition by transitioning SDA from low to high while SCL is high. The bus is then free for another transmission (Figure 3).
Bit Transfer
One data bit is transferred during each clock pulse. The data on SDA must remain stable while SCL is high (Figure 4).
Acknowledge
The acknowledge bit is a clocked 9th bit, which the recipient uses to handshake receipt of each byte of data (Figure 5). Thus, each byte transferred effectively requires 9 bits. The master generates the 9th clock pulse, and the recipient pulls down SDA during the acknowledge clock pulse, such that the SDA line is stable low during the high period of the clock pulse. When the master is transmitting to the MAX7300, the MAX7300 generates the acknowledge bit since the
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2-Wire-Interfaced, 2.5V to 5.5V, 20-Port or 28-Port I/O Expander MAX7300
CONFIGURATION
PORT REGISTERS MASK REGISTER
P4 TO P31
GPIO PORT CHANGE DETECTOR
CONFIGURATION REGISTERS DATA 8 CE R/W
GPIO DATA R/W 8
AD0 AD1
ADDRESS MATCHER
COMMAND REGISTER DECODE
7
8
8
DATA BYTE
COMMAND BYTE
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
7 7-BIT DEVICE ADDRESS SDA SCL SLAVE ADDRESS BYTE R/W
TO/FROM DATA REGISTERS
TO COMMAND REGISTERS
DATA BYTE
COMMAND BYTE
Figure 1. MAX7300 Functional Diagram
MAX7300 is the recipient. When the MAX7300 is transmitting to the master, the master generates the acknowledge bit since the master is the recipient.
addresses (Table 3), and therefore a maximum of 16 MAX7300 devices can share the same interface.
Slave Address
The MAX7300 has a 7-bit-long slave address (Figure 6). The eighth bit following the 7-bit slave address is the R/ W bit. It is low for a write command and high for a read command. The first 3 bits (MSBs) of the MAX7300 slave address are always 100. Slave address bits A3, A2, A1, and A0 are selected by the address inputs, AD1 and AD0. These two input pins can be connected to GND, V+, SDA, or SCL. The MAX7300 has 16 possible slave
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Message Format for Writing the MAX7300
A write to the MAX7300 comprises the transmission of the MAX7300's slave address with the R/ W bit set to zero, followed by at least 1 byte of information. The first byte of information is the command byte. The command byte determines which register of the MAX7300 is to be written by the next byte, if received. If a STOP condition is detected after the command byte is received, then the MAX7300 takes no further action (Figure 7) beyond storing the command byte.
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2-Wire-Interfaced, 2.5V to 5.5V, 20-Port or 28-Port I/O Expander MAX7300
SDA
tBUF tSU, DAT tLOW SCL tHD, DAT tSU, STA tHD, STA tSU, STO
tHIGH tHD, STA tR START CONDITION tF REPEATED START CONDITION STOP CONDITION START CONDITION
Figure 2. 2-Wire Serial Interface Timing Details
SDA
SCL
S START CONDITION
P STOP CONDITION
Figure 3. Start and Stop Conditions
SDA
SCL DATA LINE STABLE; DATA VALID CHANGE OF DATA ALLOWED
Figure 4. Bit Transfer
Any bytes received after the command byte are considered data bytes. The first data byte goes into the internal register of the MAX7300 selected by the command byte (Figure 8). If multiple data bytes are transmitted before a STOP condition is detected, these bytes are generally stored in subsequent MAX7300 internal registers because the command byte address generally autoincrements (Table 4).
Message Format for Reading
The MAX7300 is read using the MAX7300's internally stored command byte as address pointer, the same way the stored command byte is used as address pointer for
a write. The pointer generally autoincrements after each data byte is read using the same rules as for a write (Table 4). Thus, a read is initiated by first configuring the MAX7300's command byte by performing a write (Figure 7). The master can now read `n' consecutive bytes from the MAX7300, with the first data byte being read from the register addressed by the initialized command byte (Figure 9). When performing read-after-write verification, remember to reset the command byte's address because the stored control byte address generally has been autoincremented after the write (Table 4). Table 5 is the register address map.
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2-Wire-Interfaced, 2.5V to 5.5V, 20-Port or 28-Port I/O Expander MAX7300
START CONDITION SCL 1 2 8 9 CLOCK PULSE FOR ACKNOWLEDGMENT
SDA BY TRANSMITTER
S SDA BY RECEIVER
Figure 5. Acknowledge
SDA 1 MSB SCL 0 0 A3 A2 A1 A0 LSB R/W ACK
Figure 6. Slave Address
Operation with Multiple Masters
If the MAX7300 is operated on a 2-wire interface with multiple masters, a master reading the MAX7300 should use a repeated start between the write, which sets the MAX7300's address pointer, and the read(s) that takes the data from the location(s). This is because it is possible for master 2 to take over the bus after master 1 has set up the MAX7300's address pointer, but before master 1 has read the data. If master 2 subsequently changes, the MAX7300's address pointer, then master 1's delayed read can be from an unexpected location.
Initial Power-Up
On initial power-up, all control registers are reset and the MAX7300 enters shutdown mode (Table 6). Transition (Port Data Change) Detection Port transition detection allows seven maskable ports P24 to P30 to be continuously monitored for changes in their logic status (Figure 10). Enable transition detection by setting the M bit in the configuration register (Table 9) after setting the mask register. If port 31 is configured as an output (Tables 1 and 2), then P31 automatically becomes an interrupt request (IRQ) output to flag detected transitions. Port 31 can be configured and used as a general-purpose input port instead, if not required for use as the IRQ output. The mask register determines which of the seven ports P24 to P30 are monitored (Table 10). Set the appropriate mask bit to enable that port for transition detect. Clear the mask bit if transitions on that port are to be ignored by the transition detection logic. Ports are monitored regardless of their I/O configuration, both input and output.
Command Address Autoincrementing
Address autoincrementing allows the MAX7300 to be configured with the shortest number of transmissions by minimizing the number of times the command address needs to be sent. The command address stored in the MAX7300 generally increments after each data byte is written or read (Table 4).
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2-Wire-Interfaced, 2.5V to 5.5V, 20-Port or 28-Port I/O Expander MAX7300
COMMAND BYTE IS STORED ON RECEIPT OF STOP CONDITION ACKNOWLEDGE FROM MAX7300 S SLAVE ADDRESS R/W 0 A D15 D14 D13 D12 D11 D10 D9 D8
COMMAND BYTE ACKNOWLEDGE FROM MAX7300
A
P
Figure 7. Command Byte Received
ACKNOWLEDGE FROM MAX7300 HOW COMMAND BYTE AND DATA BYTE MAP INTO MAX7300's REGISTER ACKNOWLEDGE FROM MAX7300 S SLAVE ADDRESS R/W 0 A D15 D14 D13 D12 D11 D10 D9 D8 D7 D6
ACKNOWLEDGE FROM MAX7300 D5 D4 D3 D2 D1 D0
COMMAND BYTE
A
DATA BYTE 1 BYTE AUTOINCREMENT MEMORY WORD ADDRESS
A
P
Figure 8. Command and Single Data Byte Received
The MAX7300 maintains an internal 7-bit snapshot register to hold the comparison copy of the logic states of ports P24 to P30. The snapshot register is updated with the condition of P24 to P31 whenever the configuration register is written with the M bit set. The update action occurs regardless of the previous state of the M bit so that it is not necessary to clear the M bit and then reset it in order to update the snapshot register. When the data change detection bit is set, the MAX7300 continuously compares the snapshot register against the changing states of P24 to P31. When a difference occurs, the IRQ bit (mask register bit D7) is set and IRQ port P31 goes high if it is configured as an output. The IRQ bit and IRQ output remain set until the mask register is next read or written, so if the IRQ is set, then the mask register reads with bit D7 set. Writing the mask register clears the IRQ bit and resets the IRQ output, regardless of the value of bit D7 written. External Component RISET The MAX7300 uses an external resistor, RISET, to set internal biasing. Use a resistor value of 39k.
Applications Information
Low-Voltage Operation
The MAX7300 operates down to 2V supply voltage (although the sourcing and sinking currents are not guaranteed), providing that the MAX7300 is powered up initially to at least 2.5V to trigger the device's internal reset.
Power-Supply Considerations
The MAX7300 operates with power-supply voltages of 2.5V to 5.5V. Bypass the power supply to GND with a 0.047F capacitor as close to the device as possible. Add a 1F capacitor if the MAX7300 is far away from the board's input bulk decoupling capacitor.
Chip Information
TRANSISTOR COUNT: 33,559 PROCESS: CMOS
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2-Wire-Interfaced, 2.5V to 5.5V, 20-Port or 28-Port I/O Expander MAX7300
ACKNOWLEDGE FROM MAX7300 HOW COMMAND BYTE AND DATA BYTE MAP INTO MAX7300's REGISTER ACKNOWLEDGE FROM MAX7300 S SLAVE ADDRESS R/W 0 A COMMAND BYTE A DATA BYTE `n' BYTES AUTOINCREMENT MEMORY WORD ADDRESS A P D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 ACKNOWLEDGE FROM MAX7300 D5 D4 D3 D2 D1 D0
Figure 9. `n' Data Bytes Received
Table 3. MAX7300 Address Map
PIN CONNECTION AD1 GND GND GND GND V+ V+ V+ V+ SDA SDA SDA SDA SCL SCL SCL SCL AD0 GND V+ SDA SCL GND V+ SDA SCL GND V+ SDA SCL GND V+ SDA SCL A6 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 A5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 A4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DEVICE ADDRESS A3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 A2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 A1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 A0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
Table 4. Autoincrement Rules
COMMAND BYTE ADDRESS RANGE x0000000 to x1111110 x1111111 AUTOINCREMENT BEHAVIOR Command address autoincrements after byte read or written Command address remains at x1111111 after byte written or read
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2-Wire-Interfaced, 2.5V to 5.5V, 20-Port or 28-Port I/O Expander MAX7300
Table 5. Register Address Map
REGISTER No-Op Configuration Transition Detect Mask Factory Reserved; do not write to this port Port Configuration P7, P6, P5, P4 Port Configuration P11, P10, P9, P8 Port Configuration P15, P14, P13, P12 Port Configuration P19, P18, P17, P16 Port Configuration P23, P22, P21, P20 Port Configuration P27, P26, P25, P24 Port Configuration P31, P30, P29, P28 Port 0 only (virtual port, no action) Port 1 only (virtual port, no action) Port 2 only (virtual port, no action) Port 3 only (virtual port, no action) Port 4 only Port 5 only Port 6 only Port 7 only Port 8 only Port 9 only Port 10 only Port 11 only Port 12 only Port 13 only Port 14 only Port 15 only Port 16 only Port 17 only Port 18 only Port 19 only Port 20 only Port 21 only Port 22 only Port 23 only Port 24 only Port 25 only COMMAND ADDRESS D15 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X D14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 D13 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 D12 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 D11 0 0 0 0 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 D10 0 1 1 1 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 D9 0 0 1 1 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 D8 0 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 HEX CODE 0x00 0x04 0x06 0x07 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39
______________________________________________________________________________________
13
2-Wire-Interfaced, 2.5V to 5.5V, 20-Port or 28-Port I/O Expander MAX7300
Table 5. Register Address Map (continued)
REGISTER Port 26 only Port 27 only Port 28 only Port 29 only Port 30 only Port 31 only 4 ports 4-7 (data bits D0-D3) 5 ports 4-8 (data bits D0-D4) 6 ports 4-9 (data bits D0-D5) 7 ports 4-10 (data bits D0-D6) 8 ports 4-11 8 ports 5-12 8 ports 6-13 8 ports 7-14 8 ports 8-15 8 ports 9-16 8 ports 10-17 8 ports 11-18 8 ports 12-19 8 ports 13-20 8 ports 14-21 8 ports 15-22 8 ports 16-23 8 ports 17-24 8 ports 18-25 8 ports 19-26 8 ports 20-27 8 ports 21-28 8 ports 22-29 8 ports 23-30 8 ports 24-31 7 ports 25-31 6 ports 26-31 5 ports 27-31 4 ports 28-31 3 ports 29-31 2 ports 30-31 1 port 31 only COMMAND ADDRESS D15 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X D14 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 D13 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 D12 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 D11 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 D10 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 D9 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 D8 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 HEX CODE 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F
Note: Unused bits read as zero.
14
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2-Wire-Interfaced, 2.5V to 5.5V, 20-Port or 28-Port I/O Expander MAX7300
Table 6. Power-Up Configuration
REGISTER FUNCTION Port Register Bits 4 to 31 Configuration Register Input Mask Register Port Configuration Port Configuration Port Configuration Port Configuration Port Configuration Port Configuration Port Configuration POWER-UP CONDITION ADDRESS CODE (HEX) 0x24 to 0x3F 0x04 REGISTER DATA D7 X D6 X D5 X D4 X D3 X D2 X D1 X D0 0
GPIO Output Low Shutdown Enabled Transition Detection Disabled All Clear (Masked Off) P7, P6, P5, P4: GPIO Inputs without Pullup P11, P10, P9, P8: GPIO Inputs without Pullup P15, P14, P13, P12: GPIO Inputs without Pullup P19, P18, P17, P16: GPIO Inputs without Pullup P23, P22, P21, P20: GPIO Inputs without Pullup P27, P26, P25, P24: GPIO Inputs without Pullup P31, P30, P29, P28: GPIO Inputs without Pullup
0
0
X
X
X
X
X
0
0x06 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F
X 1 1 1 1 1 1 1
0 0 0 0 0 0 0 0
0 1 1 1 1 1 1 1
0 0 0 0 0 0 0 0
0 1 1 1 1 1 1 1
0 0 0 0 0 0 0 0
0 1 1 1 1 1 1 1
0 0 0 0 0 0 0 0
X = unused bits; if read, zero results.
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15
2-Wire-Interfaced, 2.5V to 5.5V, 20-Port or 28-Port I/O Expander MAX7300
Table 7. Configuration Register Format
FUNCTION Configuration Register ADDRESS CODE (HEX) 0x04 REGISTER DATA D7 M D6 0 D5 X D4 X D3 X D2 X D1 X D0 S
Table 8. Shutdown Control (S Data Bit D0) Format
FUNCTION Shutdown Normal Operation ADDRESS CODE (HEX) 0x04 0x04 REGISTER DATA D7 M M D6 0 0 D5 X X D4 X X D3 X X D2 X X D1 X X D0 0 1
Table 9. Transition Detection Control (M Data Bit D7) Format
FUNCTION Disabled Enabled ADDRESS CODE (HEX) 0x04 0x04 REGISTER DATA D7 0 1 D6 0 0 D5 X X D4 X X D3 X X D2 X X D1 X X D0 S S
Table 10. Transition Detection Mask Register
FUNCTION REGISTER ADDRESS (HEX) READ/ WRITE Read 0x06 Write Unchanged REGISTER DATA D7 IRQ Status* D6 Port 30 mask D5 Port 29 mask D4 Port 28 mask D3 Port 27 mask D2 Port 26 mask D1 Port 25 mask D0 Port 24 mask
Mask Register
*IRQ is automatically cleared after it is read.
16
______________________________________________________________________________________
2-Wire-Interfaced, 2.5V to 5.5V, 20-Port or 28-Port I/O Expander MAX7300
GPIO INPUT CONDITIONING GPIO/PORT OUTPUT LATCH
GPIO IN
GPIO/PORT OUT IRQ STATUS STORED AS MSB OF MASK REGISTER
P31 IRQ OUTPUT LATCH R S CLOCK PULSE AFTER EACH READ ACCESS TO MASK REGISTER
CONFIGURATION REGISTER M BIT = 1 GPIO INPUT CONDITIONING P30 GPIO/PORT OUTPUT LATCH GPIO INPUT CONDITIONING P29 GPIO/PORT OUTPUT LATCH GPIO INPUT CONDITIONING P28 GPIO/PORT OUTPUT LATCH GPIO IN GPIO IN D GPIO/PORT OUT Q MASK REGISTER BIT 4 GPIO IN GPIO IN D GPIO/PORT OUT Q MASK REGISTER BIT 6
D
Q MASK REGISTER BIT 5
GPIO/PORT OUT
GPIO INPUT CONDITIONING P27 GPIO/PORT OUTPUT LATCH GPIO INPUT CONDITIONING P26 GPIO/PORT OUTPUT LATCH GPIO INPUT CONDITIONING P25 GPIO/PORT OUTPUT LATCH
D
Q MASK REGISTER BIT 3
OR
GPIO/PORT OUT
GPIO IN D GPIO/PORT OUT Q MASK REGISTER BIT 2
GPIO IN
D
Q MASK REGISTER BIT 1
GPIO/PORT OUT
GPIO INPUT CONDITIONING P24 GPIO/PORT OUTPUT LATCH
GPIO IN D GPIO/PORT OUT Q MASK REGISTER LSB CLOCK PULSE WHEN WRITING CONFIGURATION REGISTER WITH M BIT SET
Figure 10. Maskable GPIO Ports P24 to P31
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17
2-Wire-Interfaced, 2.5V to 5.5V, 20-Port or 28-Port I/O Expander MAX7300
Pin Configurations (continued)
TOP VIEW
GND GND GND ISET V+ AD1 SCL SDA
37 36 35 34 33 32
40
39
38
ISET 1 GND GND AD0 P8 P12 P9 P13 P10 2 3 4 5 6 7 8 9
36 V+ 35 AD1 34 SCL 33 SDA 32 P4 P8 P12 P9 P13 P10 P14 P11 P15 P16 P17
1 2 3 4 5 6 7 8 9 10
31
N.C.
AD0
30 29 28 27 26
P4 P31 P5 P30 P6 P29 P7 P28 P27 P26
MAX7300
31 P31 30 P5 29 P30 28 P6 27 P29 26 P7 25 P28 24 P27 23 P26 22 P25 21 P24 20 P23 19 P22
MAX7300
25 24 23 22 21
P14 10 P11 11 P15 12 P16 13 P17 14 P18 15 P19 16 P20 17 P21 18
11
12
13
14
15
16
17
18
19
N.C.
QFN
SSOP
18
______________________________________________________________________________________
P25 N.C.
P18 P19 P20 P21 P22 P23
P24
20
2-Wire-Interfaced, 2.5V to 5.5V, 20-Port or 28-Port I/O Expander
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
SSOP.EPS
MAX7300 MAX7300
2
1
INCHES DIM A A1 B C E H D E e H L MIN 0.068 0.002 0.010 MAX 0.078 0.008 0.015
MILLIMETERS MIN 1.73 0.05 0.25 MAX 1.99 0.21 0.38 D D D D D INCHES MIN 0.239 0.239 0.278 0.317 0.397 MAX 0.249 0.249 0.289 0.328 0.407 MILLIMETERS MIN 6.07 6.07 7.07 8.07 10.07 MAX 6.33 6.33 7.33 8.33 10.33 N 14L 16L 20L 24L 28L
0.20 0.09 0.004 0.008 SEE VARIATIONS 0.205 0.301 0.025 0 0.212 0.311 0.037 8 5.20 7.65 0.63 0 5.38 7.90 0.95 8 0.0256 BSC 0.65 BSC
N
A C B e D A1 L
NOTES: 1. D&E DO NOT INCLUDE MOLD FLASH. 2. MOLD FLASH OR PROTRUSIONS NOT TO EXCEED .15 MM (.006"). 3. CONTROLLING DIMENSION: MILLIMETERS. 4. MEETS JEDEC MO150. 5. LEADS TO BE COPLANAR WITHIN 0.10 MM.
PROPRIETARY INFORMATION TITLE:
PACKAGE OUTLINE, SSOP, 5.3 MM
APPROVAL DOCUMENT CONTROL NO. REV.
21-0056
1 1
C
______________________________________________________________________________________
19
2-Wire-Interfaced, 2.5V to 5.5V, 20-Port or 28-Port I/O Expander MAX7300
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.) 36L,40L, QFN.EPS 20 ______________________________________________________________________________________
2-Wire-Interfaced, 2.5V to 5.5V, 20-Port or 28-Port I/O Expander
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
MAX7300
U
______________________________________________________________________________________
21
2-Wire-Interfaced, 2.5V to 5.5V, 20-Port or 28-Port I/O Expander MAX7300
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
SSOP.EPS
REV.
36
INCHES DIM A A1 B C e E H L D MAX MIN 0.104 0.096 0.004 0.011 0.017 0.012 0.013 0.009 0.0315 BSC 0.299 0.291 0.398 0.414 0.040 0.020 0.598 0.612
MILLIMETERS MAX MIN 2.65 2.44 0.29 0.10 0.44 0.30 0.23 0.32 0.80 BSC 7.40 7.60 10.11 10.51 0.51 15.20 1.02 15.55
E
H
1
TOP VIEW
D A1 e A
C 0-8
B
L
FRONT VIEW
SIDE VIEW
PROPRIETARY INFORMATION TITLE:
PACKAGE OUTLINE, 36L SSOP, 0.80 MM PITCH
APPROVAL DOCUMENT CONTROL NO.
21-0040
E
1 1
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
22 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2003 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

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